256kx1 static ram cy7c197 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 october 4, 1999 features ? high speed ?12 ns cmos for optimum speed/power low active power ?880 mw low standby power ?220 mw ttl-compatible inputs and outputs automatic power-down when deselected functional description the cy7c197 is a high-performance cmos static ram orga- nized as 256k words by 1 bit. easy memory expansion is pro- vided by an active low chip enable (ce ) and three-state driv- ers. the cy7c197 has an automatic power-down feature, reducing the power consumption by 75% when deselected. writing to the device is accomplished when the chip enable (ce ) and write enable (we ) inputs are both low. data on the input pin (d in ) is written into the memory location specified on the address pins (a 0 through a 17 ). reading the device is accomplished by taking chip enable (ce ) low while write enable (we ) remains high. under these conditions the contents of the memory location specified on the address pins will appear on the data output (d out ) pin. the output pin stays in a high-impedance state when chip enable (ce ) is high or write enable (we ) is low. the cy7c197 utilizes a die coat to insure alpha immunity. we gnd 28 logic block diagram pin configurations 1024 x 256 array a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps power down we ce 4 5 6 7 8 9 10 321 27 1314151617 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view dip/soj 7c197 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 ce v cc a 17 a 16 a 15 a 14 a 11 a 10 a 9 d in a 13 a 12 d out 11 12 19 18 a 2 v cc a 3 a 4 a 5 a 6 a 7 a 8 nc a 9 gnd we 7c197 top view lcc 12 13 input buffer do di a 0 a 9 a 10 a 11 a 12 a 17 a 16 a 15 a 14 a 13 ce d in a 1 a 0 a 17 nc nc nc d out a 16 a 15 a 14 a 11 a 10 a 13 a 12 c197-1 c197-2 c197-3 selection guide 7c197-12 7c197-15 7c197-20 7c197-25 7c197-35 7c197-45 maximum access time (ns) 12 15 20 25 35 45 maximum operating current (ma) 150 140 135 95 95 maximum standby current (ma) 30 30 30 30 30 30
cy7c197 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .....................................? 65 c to +150 c ambient temperature with power applied ..................................................? 55 c to +125 c supply voltage to ground potential (pin 24 to pin 12) .................................................? 0.5v to +7.0v dc voltage applied to outputs in high z state [1] ....................................... ? 0.5v to v cc + 0.5v dc input voltage [1] .................................... ? 0.5v to v cc + 0.5v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c197-12 7c197-15 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min. i ol =12.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc +0.3v v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 5+5 ? 5+5 a i oz output leakage current gnd < v o < v cc , output disabled ? 5+5 ? 5+5 a i os output short circuit current [2] v cc = max., v out = gnd ? 300 ? 300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 150 140 ma i sb1 automatic ce power-down current ? ttl inputs [3] max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 30 ma i sb2 automatic ce power-down current ? cmos inputs [3] max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 10 10 ma notes: 1. v (min.) = ? 2.0v for pulse durations of less than 20 ns. 2. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. 3. a pull-up resistor to v cc on the ce input is required to keep the device deselected during v cc power-up, otherwise i sb will exceed values given.
cy7c197 3 electrical characteristics over the operating range (continued) parameter description test conditions 7c197-20 7c197-25, 35, 45 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min. i ol =12.0ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 5 +5 ? 5 +5 a i oz output leakage current gnd < v o < v cc , output disabled ? 5 +5 ? 5 +5 a i os output short circuit current [2] v cc = max., v out = gnd ? 300 ? 300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 135 95 ma i sb1 automatic ce power down current ? ttl inputs [3] max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 30 ma i sb2 automatic ce power-down current ? cmos inputs [3] max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 15 15 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 8 pf c out output capacitance 10 pf ac test loads and waveforms [5] notes: 4. tested initially and after any design or process changes that may affect these parameters. 5. t r = < 3 ns for the -12 and -15 speeds. t r = < 5 ns for the -20 and slower speeds. r2 255 ? (255 ? mil) r1 329 ? 3.0v 5v output r1 329 ? r2 202 ? (255 ? mil) 30 pf including jig and scope gnd 90% 10% 90% 10% cy7c197 4 switching characteristics over the operating range [6] parameter description 7c197-12 7c197-15 7c197-20 7c197-25 7c197-35 7c197-45 unit min. max. min. max. min. max. min. max. min. max. min. max. read cycle t rc read cycle time 12 15 20 25 35 45 ns t aa address to data valid 12 15 20 25 35 45 ns t oha output hold from address change 3 3 3 3 3 3 ns t ace ce low to data valid 12 15 20 25 35 45 ns t lzce ce low to low z [7] 3 3 3 3 3 3 ns t hzce ce high to high z [7, 8] 5 7 0 9 0 11 0 15 0 15 ns t pu ce low to power-up 0 0 0 0 0 0 ns t pd ce high to power-down 12 15 20 20 25 30 ns write cycle [9] t wc write cycle time 12 15 20 25 35 45 ns t sce ce low to write end 9 10 15 20 30 40 ns t aw address set-up to write end 9 10 15 20 30 40 ns t ha address hold from write end 0 0 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 0 0 ns t pwe we pulse width 8 9 15 20 25 30 ns t sd data set-up to write end 8 9 10 15 17 20 ns t hd data hold from write end 0 0 0 0 0 0 ns t lzwe we high to low z [7] 2 2 3 3 3 3 ns t hzwe we low to high z [7,8] 7 7 0 10 0 11 0 15 0 15 ns notes: 6. test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower spee ds, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 7. at any given temperature and voltage condition, t hzce is less than t lzce and t hzwe is less than t lzwe for any given device. 8. t hzce and t hzwe are specified with c l = 5 pf as in part (b) in ac test loads and waveforms. transition is measured 500 mv from steady-state voltage. 9. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write.
cy7c197 5 switching waveforms notes: 10. we is high for read cycle. 11. device is continuously selected, ce = v il . read cycle no. 1 address data out previous data valid data valid t rc t aa t oha c197-6 [10, 11] read cycle no. 2 50% 50% data valid t rc t ace t lzce t pu data out high impedance impedance icc isb t hzce t pd ce high v cc supply current c197-7 [10] write cycle no.1 (we controlled) t wc data valid data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t lzwe t sd ce we data in data out address c197-8 [9]
cy7c197 6 note: 12. if ce goes high simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) write cycle no. 2 (ce controlled) t wc data valid high impedance t sce t aw t sa t pwe t ha t hd t sd address ce we data in data out c197-9 [9, 12]
cy7c197 7 typical dc and ac characteristics 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 ? 55 25 125 -55 25 125 1.2 1.0 0.8 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage(v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature( c) normalized supply current vs. ambient temperature ambient temperature( c) output voltage(v) output source current vs. output voltage 0.0 0.8 1.4 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t supply voltage(v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.01.0 2.03.04.0 output sink current (ma) 0 80 output voltage(v) output sink current vs. output voltage 0.6 0.4 0.2 0.0 normalized i , i cc sb normalized i , i cc sb i sb i cc i cc v cc =5.0v v cc =5.0v t a =25 c v cc =5.0v t a =25 c i sb t a =25 c 0.6 0.8 0 aa 1.3 1.2 v in =5.0v t a =25 c 1.4 v cc =5.0v v in =5.0v 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage (v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.0 5.0 0.0 1000 0.50 v cc =4.5v t a =25 c v cc =5.0v t a =25 c v in =0.5v
cy7c197 8 document #: 38 ? 00078 ? m cy7c197 truth table ce we input/output mode h x high z deselect/power-down l h data out read l l data in write ordering information speed (ns) ordering code package name package type operating range 12 cy7c197-12pc p13 24-lead (300-mil) molded dip commercial cy7c197-12vc v13 24-lead molded soj 15 cy7c197-15pc p13 24-lead (300-mil) molded dip commercial cy7c197-15vc v13 24-lead molded soj 20 cy7c197-20pc p13 24-lead (300-mil) molded dip commercial cy7c197-20vc v13 24-lead molded soj 25 cy7c197-25pc p13 24-lead (300-mil) molded dip commercial cy7c197-25vc v13 24-lead molded soj 35 cy7c197-35pc p13 24-lead (300-mil) molded dip commercial cy7c197-35vc v13 24-lead molded soj 45 cy7c197-45pc p13 24-lead (300-mil) molded dip commercial cy7c197-45vc v13 24-lead molded soj
package diagrams 51-85013-a 24-lead (300-mil) molded dip p13/p13a 24-lead (300-mil) molded soj v13 51-85030-a
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